1. Field of the Invention
One embodiment of the present invention relates to a semiconductor device, a method for driving the semiconductor device, a method for manufacturing the semiconductor device, and the like.
Note that the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in the specification, the drawings, and the claims (hereinafter referred to as “this specification and the like”) relates to an object, a method, or a manufacturing method. Furthermore, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, a method for driving any of them, and a method for manufacturing any of them.
2. Description of the Related Art
A latch circuit is a kind of sequential circuit and is also a kind of storage circuit capable of storing 1-bit data as “0” or “1.”
FIG. 17A is an example of a conventional latch circuit. FIG. 17B is an equivalent circuit diagram of FIG. 17A. As illustrated in FIGS. 17A and 17B, a latch circuit (LAT) 91 includes two transmission gates (92 and 93) and two inverters (94 and 95). The transmission gate 93 and the inverters 94 and 95 form a loop circuit. The phases of clock signals CLK and CLKB are inverted from each other. VDD is a high power supply potential and VSS is a low power supply potential.
In the LAT 91, an output signal of the inverter 94 is output from an output terminal out as a data signal Q. When the clock signal CLK is at a low level, an input terminal of the LAT 91 and an input node of the inverter 94 are brought into conduction, a data signal D is input to the inverter 94, and the output signal of the inverter 94 is output from the LAT 91 as the data signal Q. When the clock signal CLK is set at a high level, the input node of the inverter 94 and the input terminal of the LAT 91 are brought out of conduction, and the input node of the inverter 94 and an output node of the inverter 95 are brought into conduction. While the clock signal CLK is at a high level, the loop circuit formed by the inverters 94 and 95 retains data (state). For example, by connecting two LATs 91, a master-slave flip-flop can be formed.
A transistor in which a channel is formed in a layer of an oxide semiconductor (OS) such as an In—Ga—Zn oxide (In—Ga—Zn—O) (hereinafter such a transistor is referred to as an OS transistor) is known. In addition, it is known that an OS transistor has significantly lower off-state current than a Si transistor because an oxide semiconductor has a wider bandgap than silicon. For example, Patent Document 1 discloses a memory circuit in which an OS transistor is used as a switch.